In the preparation HgCdTe photovoltaic focal plane arrays (FPAs) for infrared (IR) imaging, the detector arrays have conventionally been fabricated separately on a bulk single crystal CdTe substrate (16), which is then indium bump bonded in a hybrid fashion to the silicon wafer containing the processing circuitry. The CdTe substrate is expensive and brittle, and frequently of poor quality.
For these reasons, sapphire, GaAs and Si substrates are in various stages of development to replace CdTe. However, the silicon multiplexer must still be bump bonded to these substrates. Such an interconnect is detrimental to the reliability, cost and flexibility of the system utilizing this IRFPA. It is therefore desirable to produce silicon signal processing circuitry on a silicon wafer and to then grow HgCdTe IR detectors on the wafer and interconnect them with the silicon circuitry. This procedure, however, presents several problems.
To begin with, it is not possible to directly grow detector quality HgCdTe on the surface of the silicon wafer. An additional problem is the interconnection of elevated detector arrays with the silicon circuitry. Because the metallic interconnections are vapor-deposited in a direction nearly normal to the wafer surface, the steep sides of the detector arrays result in poor metallic step coverage and poor interconnections.
The elevated detector arrays also severely interfere with the photolithographic process of opening up vias to the silicon circuitry for eventual interconnect between the HgCdTe array and the silicon circuitry. The interconnect between the silicon devices becomes impossible when Al rather than a refractory metal is used to interconnect the silicon devices to one another, as the Al must be deposited after the GaAs, CdTe, and HgCdTe growth, and these vias require an even more precise photolithographic process.
References in this field include the following: U.S. Pat. No. 3,793,712, which describes a method of forming areas of different silicon crystal orientation in recesses of a silicon substrate; U.S. Pat. No. 3,988,774 which deals with the manufacture of HgCdTe IR detectors on top of a substrate surface; U.S. Pat. No. 141,765 which deals with a method for making flat silicon troughs in a substrate in the production of MOS transistors; U.S. Pat. No. 4,251,299 which deals with refilling grooves in a silicon substrate using liquid phase epitaxial growth from a tin melt; U.S. Pat. No. 4,312,115 in which separate IR detectors are formed on a chip by etching from both sides of the chip; U.S. Pat. No. 4,376,663 which discloses a method of growing CdTe on HgCdTe by liquid phase epitaxy; U.S. Pat. No. 4,646,120 which avoids cross talk through the use of grooves on the outside of the HgCdTe and layers not responsive to IR radiation; Japanese Patent No. 55-22866 which deals with the production of flat MOS circuitry; and Japanese Patent No. 56-49581 which deals with growing a P-N junction in a photodiode involving CdTe on silicon.